Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA-Reference-Cited by-同舟云学术

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Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA

Published:2022-12 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Smart Electronic Systems (iSES)
language:
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Author:

Chandrasekhar B S¹,Deepanjali S²,Sk Noor Mahammad²

Affiliation:

1. University of Mysore,Dept. Studies in CS.,Mysore,India

2. IIITDM Kancheepuram,Dept. CSE.,Chennai,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10026847/10026888/10026912.pdf?arnumber=10026912

Reference16 articles.

1. LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs

2. Low cost convolutional code based concurrent error detection in FSMs

3. A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs

4. Improved Hamming Code for Error Detection and Correction

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