Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications
Author:
Affiliation:
1. Institute of Electrical and Computer Engineering
2. National Yang Ming Chiao Tung University,Institute of Electrical and Control Engineering,Hsinchu,Taiwan,30010
Funder
National Science and Technology Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10094038/10094053/10094078.pdf?arnumber=10094078
Reference11 articles.
1. The impact of intrinsic device fluctuations on CMOS SRAM cell stability
2. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications
3. Matching properties of MOS transistors
4. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors;khwa;ISSCC Dig Tech Papers,2018
5. A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS;2023 IEEE International Test Conference in Asia (ITC-Asia);2023-09-12
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