A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support-Reference-Cited by-同舟云学术

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A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support

Published:2011-12 Issue: Volume: Page:
ISSN:
Container-title:2011 International Symposium on Electronic System Design
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Author:

Baluni Alok,Merchant Farhad,Nandy S.K.,Balakrishnan S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6117294/6117297/06117324.pdf?arnumber=6117324

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division;Applied Sciences;2021-05-28

2. Design of quadruple precision multiplier architectures with SIMD single and double precision support;Integration;2019-03

3. Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2018

4. Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-02

5. Configurable Architectures for Multi-Mode Floating Point Adders;IEEE Transactions on Circuits and Systems I: Regular Papers;2015-08

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