Time domain enhancement of tab-routed microstrip line with EMC validation for DDR4 memory design
Author:
Affiliation:
1. NIT,Department of ECE,Kurukshetra,Haryana
2. NIT,Department of ECE,Kurukshetra
3. Edge Platform Engineering, Intel Technology India Pvt. Ltd.,Bangalore
4. Network & EDGE computing, Intel Technology India Pvt. Ltd.,Bangalore
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10463756/10463710/10464156.pdf?arnumber=10464156
Reference11 articles.
1. Analysis of Power Supply And Signal Integrity of High Speed PCB Board
2. Desense Prediction and Mitigation from DDR Noise Source
3. DDR RF Interference in Fan-less SoC Design
4. Signal Integrity and Power Integrity Challenges in Embedded Computing Boards
5. Enhanced Power and Signal Integrity Through Layout Optimization of High-Speed Memory Systems
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