Pareto Optimal Design Space Exploration for Accelerated CNN on FPGA
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8765855/8778198/08778248.pdf?arnumber=8778248
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A design space exploration framework for deployment of resource-constrained deep neural networks;Real-Time Image Processing and Deep Learning 2024;2024-06-07
2. Design Space Exploration in the Physical-Design of an AI-Processor at 12 nm Using Relative-Placement Methodology;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
3. Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA;2022 32nd International Conference on Field-Programmable Logic and Applications (FPL);2022-08
4. A Parallelism Strategy Optimization Search Algorithm Based on Three-dimensional Deformable CNN Acceleration Architecture;J ELECTRON INF TECHN;2022
5. AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators;ACM Transactions on Design Automation of Electronic Systems;2022-02-12
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