Author:
Guidi Giulia,Reggiani Enrico,Di Tucci Lorenzo,Durelli Gianluca,Blott Michaela,Santambrogio Marco D.
Cited by
17 articles.
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1. Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation;IEEE Transactions on Parallel and Distributed Systems;2022-06-01
2. A Survey on System-on-a-Chip Design Using Chisel HW Construction Language;IECON 2021 – 47th Annual Conference of the IEEE Industrial Electronics Society;2021-10-13
3. Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs;2020 IEEE 33rd International System-on-Chip Conference (SOCC);2020-09-08
4. Accelerating Face Detection Algorithm on the FPGA Using SDAccel;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2020
5. A scala based framework for developing acceleration systems with FPGAs;Journal of Systems Architecture;2019-09