Current-gain enhancement in lateral p-n-p transistors by an optimized gap in the n+buried layer
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx5/16/31761/01478902.pdf?arnumber=1478902
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A simple technique for improving lateral p-n-p transistor performance;IEEE Journal of Solid-State Circuits;1982-08
2. Analytical solutions for the breakdown voltages of punched-through diodes having curved junction boundaries at the edges;IEEE Transactions on Electron Devices;1980-05
3. Current gain in bipolar transistors with a field plate over the base surface;IEE Proceedings I Solid State and Electron Devices;1980
4. The lateral p-n-p transistor—A practical investigation of the DC characteristics;IEEE Transactions on Electron Devices;1979-07
5. Transverse diffusion in planar transistors;IEEE Transactions on Electron Devices;1978-01
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