Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process-Reference-Cited by-同舟云学术

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Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

Published:2006-10 Issue:10 Volume:53 Page:2187-2193
ISSN:1057-7122
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Ker M.-D.,Chen W.-Y.,Hsu K.-C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/36083/01710198.pdf?arnumber=1710198

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes;IEEE Transactions on Electron Devices;2020-01

2. Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-05

3. Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology;IEEE Transactions on Circuits and Systems I: Regular Papers;2009-04

4. Design and Analysis for a 60-GHz Low-Noise Amplifier With RF ESD Protection;IEEE Transactions on Microwave Theory and Techniques;2009-02

5. ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers;IEEE Transactions on Electron Devices;2008-06

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