1- and 80-MS/s SAR ADCs in 40-nm CMOS With End-to-End Compilation
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8011414/9677053/09983835.pdf?arnumber=9983835
Reference8 articles.
1. A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS
2. A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS
3. OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler
4. A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks
5. A Systematic Design Methodology of Asynchronous SAR ADCs
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1. A 10-bit 40MS/s SAR ADC with a low-noise low-offset dynamic comparator and a high-linearity sampling switch;IEICE Electronics Express;2024-06-25
2. A Design Aid Tool for Asynchronous SAR ADCs;2024 14th International Conference on Electrical Engineering (ICEENG);2024-05-21
3. A 10-bit 40 MS/s SAR ADC With a Low-Noise Low-Offset Dynamic Comparator and a High-Linearity Sampling Switch;IEICE ELECTRON EXPR;2024
4. Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper);2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
5. Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01
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