Study of the Gate-Sensing and Channel-Sensing Transient Analysis Method for Monitoring the Charge Vertical Location of SONOS-Type Devices-Reference-Cited by-同舟云学术

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Study of the Gate-Sensing and Channel-Sensing Transient Analysis Method for Monitoring the Charge Vertical Location of SONOS-Type Devices

Published:2007-09 Issue:3 Volume:7 Page:407-419
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Pei-Ying Du ,Hang-Ting Lue ,Szu-Yu Wang ,Erh-Kun Lai ,Tiao-Yuan Huang ,Kuang-Yeu Hsieh ,Liu R.,Chih-Yuan Lu ,Pei-Ying Du

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/7298/4375320/04358687.pdf?arnumber=4358687

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory;J SEMICOND TECH SCI;2017

2. Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory;Japanese Journal of Applied Physics;2016-12-20

3. Inert ambient annealing effect on MANOS capacitor memory characteristics;Nanotechnology;2015-03-12

4. Electron-Trap and Hole-Trap Distributions in Metal/Oxide/Nitride/Oxide/Silicon Structures;IEEE Transactions on Electron Devices;2013-02

5. Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer;ECS Transactions;2011-04-25

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