Design and Implementation of Radix-4 MBW Multiplier using 45 nm technology-Reference-Cited by-同舟云学术

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Design and Implementation of Radix-4 MBW Multiplier using 45 nm technology

Published:2022-10-16 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon)
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Author:

M S Sowmyashree¹,I G Saritha¹,I.G Naveen²,Sagar K V³,Gafar Liya³,Khan Naureen³,woodi Rakshita³

Affiliation:

1. BMS Institute of Technology and Management,Electronics and Telecommunication Engineering,Bangalore,India

2. Nitte Meenakshi Institute of Technology,Department of ECE,Bengaluru,India

3. BMSIT&M,Electronics and Telecommunication Engineering,Bangalore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9972337/9971799/09972576.pdf?arnumber=9972576

Reference20 articles.

1. A Novel Parallel Multiplier for 2's Complement Numbers Using Booth's Recoding Algorithm

2. Design and Implementation of Full Adder Cell with the GDI Technique Based on 0.18?m CMOS Technology;bazzazi;The International MultiConference of Engineers and Computer Scientists,2010

3. Implementation of fast multiplier using modified Radix-4 booth algorithm with redundant binary adder for low energy applications

4. 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

5. 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

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