Author:
Mashimo Susumu,Chu Thiem Van,Kise Kenji
Cited by
40 articles.
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1. DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-05
2. A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02
3. Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
4. An Energy Efficient Sorting Architecture with Cell-Gating for Top-K Sorting on FPGA;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
5. k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-05