Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms-Reference-Cited by-同舟云学术

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Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms

Published:2017-04 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
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Author:

Morcel Raghid,Akkary Haitham,Hajj Hazem,Saghir Mazen,Keshavamurthy Anil,Khanna Rahul,Artail Hassan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7964000/7966626/07966681.pdf?arnumber=7966681

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Single Precision Floating Point Multiplier for Machine Learning Hardware Acceleration;2021 IEEE Conference on Telecommunications, Optics and Computer Science (TOCS);2021-12-10

2. MTGAN: Extending Test Case set for Deep Learning Image Classifier;IEICE Transactions on Information and Systems;2021-05-01

3. A Survey and Taxonomy of FPGA-based Deep Learning Accelerators;Journal of Systems Architecture;2019-09

4. [DL] A Survey of FPGA-based Neural Network Inference Accelerators;ACM Transactions on Reconfigurable Technology and Systems;2019-03-31

5. A New Reconfigurable Architecture with Applications to IoT and Mobile Computing;IFIP Advances in Information and Communication Technology;2019

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