Author:
Restuccia Francesco,Biondi Alessandro,Marinoni Mauro,Cicero Giorgiomaria,Buttazzo Giorgio
Cited by
27 articles.
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1. Design and Simulation of AXI4 Stream Interconnect Using Verilog;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
2. Towards Zero-Trust Hardware Architectures in Safety and Security Critical System-on-Chips;2024 IEEE 3rd Real-Time and Intelligent Edge Computing Workshop (RAGE);2024-05-13
3. AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
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5. Performance Analysis and Optimal Design of BATS Code: A Hardware Perspective;IEEE Transactions on Vehicular Technology;2023-08