BitPruner: Network Pruning for Bit-serial Accelerators
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9211868/9218488/09218534.pdf?arnumber=9218534
Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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2. Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity;IEEE Transactions on Computers;2024-01
3. A Defect-Based MEMS Phononic Crystal Slab Waveguide in Electronic Circuits;Journal of Microelectromechanical Systems;2023-10
4. AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
5. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
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