Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead-Reference-Cited by-同舟云学术

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Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead

Published:2020-07 Issue: Volume: Page:
ISSN:
Container-title:2020 57th ACM/IEEE Design Automation Conference (DAC)
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Author:

Kim Hyungjun,Kim Yulhwa,Ryu Sungju,Kim Jae-Joon

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9211868/9218488/09218657.pdf?arnumber=9218657

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. On the Structured Design Methodology of Effective PRACH Detection: Multi-Stage Thresholding Perspective;IEEE Access;2024

3. Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory;Sensors;2023-12-19

4. Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

5. The Unreasonable Effectiveness of Large Language-Vision Models for Source-free Video Domain Adaptation;2023 IEEE/CVF International Conference on Computer Vision (ICCV);2023-10-01

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