A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy
Author:
Affiliation:
1. University of Arizona,Department of Electrical & Computer Engineering,Tucson,AZ,USA
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9978287/9978272/09978335.pdf?arnumber=9978335
Reference23 articles.
1. A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory
2. Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design
3. Pinatubo
4. In-Memory Computing with Spintronic Devices
5. Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks
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1. A robust deep learning attack immune MRAM-based physical unclonable function;Scientific Reports;2024-09-04
2. STT-RAM-Based Hierarchical in-Memory Computing;IEEE Transactions on Parallel and Distributed Systems;2024-09
3. CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
4. A Study on Approximate Computing for Non-volatile Memory-Based Memory Systems;Journal of Electrical Engineering & Technology;2024-01-29
5. Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey;IEEE Access;2024
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