Author:
Ahuja Sumit,Shukla Sandeep
Cited by
11 articles.
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1. Physical and System Level Power Reduction Technique for NoC Architectures: Overview of State of the Art;2023 International Conference on Decision Aid Sciences and Applications (DASA);2023-09-16
2. Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-06
3. Dynamic Power Optimization Based on Formal Property Checking of Operations;2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID);2017-01
4. Logic Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
5. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-04