Return-limited inductances: a practical approach to on-chip inductance extraction

Author:

Shepard K.L.,Zhong Tian

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 36 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Impact of On-Die Inductance from top metal power delivery routings in HSIO & Ethernet;2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS);2021-12-13

2. Inductance Computations;Circuit Oriented Electromagnetic Modeling Using the Peec Techniques;2017-06-02

3. High-Accuracy Parasitic Extraction;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14

4. Layout Extraction;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14

5. A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures;VLSI-SoC: Technologies for Systems Integration;2011

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