FPGA Implementation of High Speed 64-Bit Data Width True Random Number Generator using Clock Managers With Metastability

Author:

Marimuthu C.N.1,Priyanka B.1

Affiliation:

1. Nandha Engineering College,Department of ECE,Erode,Tamilnadu,India

Publisher

IEEE

Reference10 articles.

1. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips;ataberk;ArXiv Preprint,2022

2. FPGA Implementation of High Speed True Random Number Generator using Clock Managers with Metastability;priyanka;International Journal of Innovative Research in Science Engineering and Technology (IJIRSET),2022

3. The advantages of the Matthews correlation coefficient (MCC) over F1 score and accuracy in binary classification evaluation;chicco;BMC Genomics,2020

4. NISQ+: Boosting quantum computing power by approximating quantum error correction;adam;2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA),2020

5. An FPGA implementation of deep spiking neural networks for low-power and fast classification;xiping;Neural Computation,2020

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