MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution-Reference-Cited by-同舟云学术

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MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution

Published:2023-01-01 Issue:1 Volume:72 Page:183-195
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Gruin Alban¹,Carle Thomas¹^ORCID,Rochange Christine¹,Casse Hugues¹,Sainrat Pascal¹

Affiliation:

1. IRIT - Univ. Toulouse 3 - CNRS, Toulouse, France

Funder

Agence Nationale de la Recherche

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/9984045/09882041.pdf?arnumber=9882041

Reference27 articles.

1. Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core

2. Design and analysis of SIC: a provably timing-predictable pipelined processor core

3. Toward Compact Abstractions for Processor Pipelines

4. Towards compositionality in execution time analysis

5. On static execution-time analysis: Compositionality, pipeline abstraction, and predictable hardware;hahn,2018

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multi-core interference over-estimation reduction by static scheduling of multi-phase tasks;Real-Time Systems;2024-09-05

2. Enabling timing predictability in the presence of store buffers;The 31st International Conference on Real-Time Networks and Systems;2023-06-07

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