PR-SSD: Maximizing Partial Read Potential By Exploiting Compression and Channel-Level Parallelism

Author:

Kang Mincheol1,Lee Wonyoung1,Kim Jinkwon1,Kim Soontae1

Affiliation:

1. School of Computing, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea

Funder

National Research Foundation of Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Reference45 articles.

1. Improving performance and lifetime of solid-state drives using hardware-accelerated compression

2. DFTL

3. Selective Compression Scheme for Read Performance Improvement on Flash Devices

4. CAFTL: A content-aware flash translation layer enhancing the lifespan of flash memory based solid state drives;chen;Proc 9th USENIX Conf File stroage Technol,2011

5. Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches;gennady pekhimenko;In International Conference on Parallel Architectures and Compilation Techniques (PACT),2012

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