Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs-Reference-Cited by-同舟云学术

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Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs

Published:2023-01-01 Issue:1 Volume:72 Page:154-167
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Restuccia Francesco¹^ORCID,Pagani Marco²,Biondi Alessandro²,Marinoni Mauro²^ORCID,Buttazzo Giorgio²^ORCID

Affiliation:

1. University of California San Diego, La Jolla, CA, USA

2. Scuola Superiore Sant’Anna, Pisa, Italy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/9984045/09917304.pdf?arnumber=9917304

Reference36 articles.

1. Xilinx. AXI Interconnect, LogiCORE IP Product Guide,2018

2. Xilinx. Zynq UltraScale Device - Reference Manual,2017

3. Xilinx. Vivado Design Suite: AXI Reference Guide,2017

4. Xilinx. AXI Performance Monitor v5.0,2017

5. Xilinx Inc. SmartConnect, LogiCORE IP Product Guide,2018

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2. FPGA-Based Digital Circuit Design for UAV Pilot-in-Loop System with Field Test Verification;2023 6th International Seminar on Research of Information Technology and Intelligent Systems (ISRITI);2023-12-11

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