Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis-Reference-Cited by-同舟云学术

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Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis

Published:2010-01 Issue: Volume: Page:
ISSN:
Container-title:2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
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Author:

Falkenstern Paul,Yuan Xie ,Yao-Wen Chang ,Yu Wang

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5415928/5419673/05419899.pdf?arnumber=5419899

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimizing Hierarchical 3-D Floorplanning with simulated annealing Algorithm;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

2. A Bridge-Based Compression Algorithm for Topological Quantum Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12

3. A Comprehensive Analysis in Recent Advances in 3D VLSI Floorplan Representations;Lecture Notes in Electrical Engineering;2022-12-01

4. A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

5. 3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies;Advances in Intelligent Systems and Computing;2020-11-24

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