Buffered clock tree synthesis for 3D ICs under thermal variations-Reference-Cited by-同舟云学术

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Buffered clock tree synthesis for 3D ICs under thermal variations

Published:2008-01 Issue: Volume: Page:
ISSN:
Container-title:2008 Asia and South Pacific Design Automation Conference
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Short-container-title:

Author:

Minz Jacob,Xin Zhao ,Sung Kyu Lim

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4480121/4483913/04484003.pdf?arnumber=4484003

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient Statistical Clock Skew Analysis Method for Clock Trees;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. 3D integration of 2D electronics;Nature Reviews Electrical Engineering;2024-04-25

3. A Hierarchical Clock Network Synthesis Method for 3D Integrated Circuits with Obstacle Avoidance;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

4. An efficient encoding technique for 3D integrated switching circuits activities;Materials Today: Proceedings;2020

5. An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC;IET Computers & Digital Techniques;2018-11-27

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