Author:
Wang Yujie,Chen Pu,Hu Jiang,Rajendran Jeyavijayan J V
Cited by
25 articles.
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1. Secure Physical Design;Hardware Security;2024
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3. Post-satisfiability Era: Countermeasures and Threats;Understanding Logic Locking;2023-09-23
4. Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
5. T-TER: Defeating A2 Trojans with Targeted Tamper-Evident Routing;Proceedings of the ACM Asia Conference on Computer and Communications Security;2023-07-10