1. An Efficient Statistical Clock Skew Analysis Method for Clock Trees;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System;2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS);2023-04-19
3. An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC;IET Computers & Digital Techniques;2018-11-27
4. Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of 3-D ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-10
5. References;Three-Dimensional Integrated Circuit Design;2017