Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs-Reference-Cited by-同舟云学术

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Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs

Published:2012-01 Issue: Volume: Page:
ISSN:
Container-title:17th Asia and South Pacific Design Automation Conference
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Author:

Chae Kwanyeob,Mukhopadhyay Saibal

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6156603/6164924/06164958.pdf?arnumber=6164958

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Voltage scaling for 3-D ICs: When, how, and how much?;Microelectronics Journal;2017-11

2. Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-05

3. Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits;IEEE Transactions on Components, Packaging and Manufacturing Technology;2014-11

4. Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis;Integration;2014-09

5. Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors;ACM Transactions on Design Automation of Electronic Systems;2014-08

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