Author:
Wu Kuan-Te,Li Jin-Fu,Lo Chih-Yen,Lai Jenn-Shiang,Kwai Ding-Ming,Chou Yung-Fa
Cited by
2 articles.
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1. Review on BIST architectures of DRAMs;2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2023-02-18
2. Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead;ACM Transactions on Design Automation of Electronic Systems;2020-09-02