Fully parallel integrated CAM/RAM using preclassification to enable large capacities
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/4/10829/00509851.pdf?arnumber=509851
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-04
2. VLSI-architecture for enabling multiple parallel associative searches with standard SRAM macros;2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS);2009-12
3. Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory;IEICE Transactions on Information and Systems;2007-01-01
4. Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey;IEEE Journal of Solid-State Circuits;2006-03
5. An FPGA Implementation of a Multi-comparand Multi-search Associative Processor;Lecture Notes in Computer Science;2002
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