Analytical jitter estimation of two-stage output buffers with supply voltage fluctuations
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6881319/6898924/06898945.pdf?arnumber=6898945
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-06
2. Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners;Sensors;2022-08-30
3. Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters;IEEE Access;2022
4. Extracting power supply current profile by using interposer-based low-noise probing technique for PDN design of high-density POP;2020 IEEE 70th Electronic Components and Technology Conference (ECTC);2020-06
5. Modeling the Combined Effects of Transmission Media and Ground Bounce on Power Supply Induced Jitter;IEEE Transactions on Electromagnetic Compatibility;2019-08
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