Modeling of real-time embedded systems using SysML and its verification using UPPAAL and DiVinE-Reference-Cited by-同舟云学术

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Modeling of real-time embedded systems using SysML and its verification using UPPAAL and DiVinE

Published:2014-06 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE 5th International Conference on Software Engineering and Service Science
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Author:

Basit-Ur-Rahim Muhammad Abdul,Arif Fahim,Ahmad Jamil

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6917618/6933501/06933529.pdf?arnumber=6933529

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel reliability redundancy allocation problem formulation for complex systems;Reliability Engineering & System Safety;2023-11

2. Formal verification of reconfigurable systems;Soft Computing;2023-05-06

3. SysML Flow Model;2022 29th Asia-Pacific Software Engineering Conference (APSEC);2022-12

4. A Formal Analysis of Moving Target Defense;2020 IEEE 44th Annual Computers, Software, and Applications Conference (COMPSAC);2020-07

5. Requirement-driven model-based development methodology applied to the design of a real-time MEG data processing unit;Software and Systems Modeling;2020-05-08

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