Technology Mapping Using Multi-Output Library Cells
Author:
Affiliation:
1. EPFL,Integrated Systems Laboratory,Lausanne,Switzerland
Funder
SNF
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10323590/10323543/10323999.pdf?arnumber=10323999
Reference20 articles.
1. A new retiming-based technology mapping algorithm for LUT-based FPGAs
2. ASAP7: A 7-nm finFET predictive process design kit;clark;Microelectronics Journal,2016
3. DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
4. Wavefront technology mapping;stok;Proc DATE,0
5. The EPFL logic synthesis libraries;soeken;CoRR,2022
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1. Technology-Aware Logic Synthesis for Superconducting Electronics;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
2. In Medio Stat Virtus*: Combining Boolean and Pattern Matching;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
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