Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems

Author:

Coskun AyseORCID,Eris Furkan,Joshi AjayORCID,Kahng Andrew B.,Ma YenaiORCID,Narayan AdityaORCID,Srinivas Vaishnav

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Multiobjective Optimization for PSIJ Mitigation and Impedance Improvement Based on PCPS/DR-NSDE in Chiplet-Based 2.5-D Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. Review of chiplet-based design: system architecture and interconnection;Science China Information Sciences;2024-07-19

3. ETRS: efficient turn restrictions setting method for boundary routers in chiplet-based systems;The Journal of Supercomputing;2024-06-01

4. Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

5. A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

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