Online Reset for Signal Temporal Logic Monitoring-Reference-Cited by-同舟云学术

Online Reset for Signal Temporal Logic Monitoring

Published:2022-11 Issue:11 Volume:41 Page:4421-4432
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Zhang Zhenya¹^ORCID,Arcaini Paolo²^ORCID,Xie Xuan³

Affiliation:

1. Faculty of Information Science and Electrical Engineering, Kyushu University, Fukuoka, Japan

2. Information Systems Architecture Science Research Division, National Institute of Informatics, Chiyoda City, Japan

3. Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada

Funder

Japan Science and Technology Agency

Japan Society for the Promotion of Science

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

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