Highly efficient test architecture for low power AI accelerators-Reference-Cited by-同舟云学术

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Highly efficient test architecture for low power AI accelerators

Published:2021 Issue: Volume: Page:1-1
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Ibtesam Muhammad,Solangi Umair Saeed,Kim Jinuk,Ansari Muhammad Adil,Park Sungju

Funder

Higher Education Commision Pakistan

Ministry of Education

National Research Foundation of Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/6917053/09530455.pdf?arnumber=9530455

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A New Zero-Overhead Test Method for Low-Power AI Accelerators;IEEE Transactions on Circuits and Systems II: Express Briefs;2023

2. Bidirectional Linear Wireless Sensor Networks;2022 International Interdisciplinary Humanitarian Conference for Sustainability (IIHC);2022-11-18

3. Recent Developments in Low-Power AI Accelerators: A Survey;Algorithms;2022-11-08

4. Cortical-inspired placement and routing: minimizing the memory resources in multi-core neuromorphic processors;2022 IEEE Biomedical Circuits and Systems Conference (BioCAS);2022-10-13

5. Wireless Sensor Network as a Mesh: Vision and Challenges;IEEE Access;2022

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