PowerSyn: A Logic Synthesis Framework with Early Power Optimization
Author:
Affiliation:
1. School of Computer Science, National Key Laboratory for Multimedia Information Processing, Peking University, Beijing, China
Funder
National Key R&D Program of China
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
http://xplorestaging.ieee.org/ielx7/43/6917053/10186351.pdf?arnumber=10186351
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1. A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses;Journal of Low Power Electronics and Applications;2024-08-05
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