Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults-Reference-Cited by-同舟云学术

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Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults

Published:2024-06 Issue:6 Volume:43 Page:1677-1690
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Somoye Idris¹^ORCID,Mannos Tom J.²^ORCID,Dziki Brian³^ORCID,Plusquellic Jim⁴^ORCID

Affiliation:

1. Sandia National Laboratories, Albuquerque, NM, USA

2. Advanced CMOS Products/Design, Sandia National Laboratories, Albuquerque, NM, USA

3. Department of Defense, Information Assurance Research, Fort Meade, MD, USA

4. Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/43/10535356/10391068.pdf?arnumber=10391068

Reference26 articles.

1. A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

2. Architectures for online error detection and recovery in multicore processors

3. DIVA: a reliable substrate for deep submicron microarchitecture design

4. Countermeasures against fault attacks: The good, the bad, and the ugly

5. AR-SMT: a microarchitectural approach to fault tolerance in microprocessors

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor;Cryptography;2024-04-22

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