A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs

Author:

Andrade Gabriel A. G.ORCID,Graf MarlesonORCID,Pfeifer NicolasORCID,dos Santos Luiz C. V.ORCID

Funder

Conselho Nacional de Desenvolvimento Científico e Tecnológico, Brazil

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, Brazil—Finance

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. UVM-based Reusable Hardware Accelerator Verification Platform;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

2. Fully-Adjustable Test Signal Generation Module with Multi-Functional Outputs;2023 IEEE 16th International Conference on Electronic Measurement & Instruments (ICEMI);2023-08-09

3. EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory Verification;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-02

4. A composite SystemC-UVM abstract optimal path selection verification architecture for complex designs;Microelectronics Reliability;2022-04

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