SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks

Author:

Yin Ruokai1ORCID,Moitra Abhishek1ORCID,Bhattacharjee Abhiroop1ORCID,Kim Youngeun1,Panda Priyadarshini1ORCID

Affiliation:

1. Department of Electrical Engineering, Yale University, New Haven, CT, USA

Funder

Technology Innovation Institute

Defense Advanced Research Projects Agency

Defense Sciences Office, DARPA

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A reconfigurable FPGA-based spiking neural network accelerator;Microelectronics Journal;2024-10

2. Efficient O-type mapping and routing of large-scale neural networks to torus-based ONoCs;Journal of Optical Communications and Networking;2024-08-23

3. Direct training high-performance deep spiking neural networks: a review of theories and methods;Frontiers in Neuroscience;2024-07-31

4. A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24

5. SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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