Enhancing Temporal Logic Falsification With Specification Transformation and Valued Booleans
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Published:2020-12
Issue:12
Volume:39
Page:5247-5260
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ISSN:0278-0070
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Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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language:
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Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
Author:
Liden Eddeland JohanORCID,
Claessen Koen,
Smallbone Nicholas,
Ramezani ZahraORCID,
Miremadi Sajed,
Akesson Knut
Funder
Swedish Governmental Agency for Innovation Systems (VINNOVA) Project
Swedish Research Council (VR) Project
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
1 articles.
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