Author:
Lee Siang-Yun,Riener Heinz,Mishchenko Alan,Brayton Robert K.,De Micheli Giovanni
Funder
Schweizerischer Nationalfonds zur Frderung der Wissenschaftlichen Forschung
cole Polytechnique Fdrale de Lausanne
SRC
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
8 articles.
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1. An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A Semi-Tensor Product based Circuit Simulation for SAT-sweeping;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
3. A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
4. Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
5. Logic Synthesis for Emerging Technologies;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24