Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models-Reference-Cited by-同舟云学术

Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models

Published:2023-04 Issue:4 Volume:42 Page:1133-1146
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

De Sayandip¹^ORCID,Shafique Muhammad²^ORCID,Corporaal Henk¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands

2. Department of Electrical and Computer Engineering, New York University Abu Dhabi, Abu Dhabi, UAE

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference39 articles.

1. Developing synthesis flows without human knowledge;yu;Proc DAC,2018

3. Fast graph representation learning with PyTorch geometric;fey;Proc ICLR Workshop Represent Learn Graphs Manifolds,2019

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. LSTP: A Logic Synthesis Timing Predictor;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22