Author:
Thou-Ho Chen ,Liang-Gee Chen
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
5 articles.
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1. Error sensitivity study of FFT architectures implemented in FPGA;Microelectronics Reliability;2021-11
2. Design-for-testability and fault-tolerant techniques for FFT processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-06
3. Implementation of the FFT butterfly with redundant arithmetic;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;1996
4. VLSI-based array dividers with concurrent error detection;International Journal of Electronics;1995-06
5. Easily testable and fault-tolerant design of FFT butterfly networks;Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).