Simulation and Extraction of Dual-Gate TFET With Ferroelectric Material to Preserve Data
Author:
Affiliation:
1. National Institute of Technology Delhi,Department of Electronics and Communication Engineering,Delhi,India,110036
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10468568/10468675/10469435.pdf?arnumber=10469435
Reference19 articles.
1. Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs
2. An Analytical Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions and the Channel Mobile Charge Carriers
3. Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability
4. An analysis on the ambipolar current in Si double-gate tunnel FETs
5. Reduction of TFET OFF-Current and Subthreshold Swing by Lightly Doped Drain
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