Power Delivery Network Benchmarking for Interposer and Bridge-Chip-Based 2.5-D Integration
Author:
Funder
NSF
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://ieeexplore.ieee.org/ielaam/55/8240809/8141982-aam.pdf
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design Considerations for Power Delivery Network and Metal-Insulator-Metal Capacitor Integration in Bridge-Chips for 2.5-D Heterogeneous Integration;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05
2. Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems;Sensors;2023-02-13
3. Analysis of Power Delivery Network (PDN) in Bridge-Chips for 2.5-D Heterogeneous Integration;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-11
4. Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs;IEEE Transactions on Electron Devices;2020-01
5. Power Delivery Network Modeling and Benchmarking for Emerging Heterogeneous Integration Technologies;IEEE Transactions on Components, Packaging and Manufacturing Technology;2019-09
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