An Object-Aware Hardware Transactional Memory System
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4637648/4637649/04637685.pdf?arnumber=4637685
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Hardware Approaches to Transactional Memory in Chip Multiprocessors;Handbook on Data Centers;2015
2. An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory;ACM Transactions on Architecture and Code Optimization;2013-01
3. SUV: A Novel Single-Update Version-Management Scheme for Hardware Transactional Memory Systems;2012 IEEE 26th International Parallel and Distributed Processing Symposium;2012-05
4. Transactional Memory, 2nd edition;Synthesis Lectures on Computer Architecture;2010-12-22
5. Improving Performance by Reducing Aborts in Hardware Transactional Memory;High Performance Embedded Architectures and Compilers;2010
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