A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8226344/8240197/08240275.pdf?arnumber=8240275
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier;IEEE Journal of Solid-State Circuits;2023-04
2. A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-07
3. A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC;IEEE Journal of Solid-State Circuits;2021-06
4. A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping;IEEE Journal of Solid-State Circuits;2021-03
5. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration;IEEE Journal of Solid-State Circuits;2021
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