A low phase noise 24/77 GHz dual-band sub-sampling PLL for automotive radar applications in 65 nm CMOS technology-Reference-Cited by-同舟云学术

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A low phase noise 24/77 GHz dual-band sub-sampling PLL for automotive radar applications in 65 nm CMOS technology

Published:2013-11 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Yi Xiang,Boon Chirn Chye,Sun Junyi,Huang Nan,Lim Wei Meng

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6679622/6690965/06691071.pdf?arnumber=6691071

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 23.7 to 29.9 GHz Tunable Fully Differential Voltage Controlled Oscillator Designed in 180nm CMOS process;2023 IEEE 16th Dallas Circuits and Systems Conference (DCAS);2023-04-14

2. An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs_rms Jitter and Fast Frequency Hopping;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-03

3. A 24 GHz hydrology radar system capable of wide‐range surface velocity detection for water resource management applications;Microwave and Optical Technology Letters;2020-06-19

4. Sub-Sampling PLL For Millimeter Wave Applications: An Overview;2019 IEEE MTT-S International Microwave Conference on Hardware and Systems for 5G and Beyond (IMC-5G);2019-08

5. A 93.4–104.8-GHz 57-mW Fractional-${N}$ Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology;IEEE Transactions on Microwave Theory and Techniques;2019-06

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