Channel Impedance Optimization For 100 Gbps High-Speed Networking Interfaces
Author:
Affiliation:
1. Dell Technologies Server Group,Taipei,Taiwan
2. Dell Technologies Server Group,Bangalore,India
3. Dell Technologies Server Group,Round Rock,TX,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9994795/9994852/09994920.pdf?arnumber=9994920
Reference7 articles.
1. COM and Reference Transmitter/Receiver/Package for 106/112Gbps Long- Reach and Chip-to-Chip Links;wu;Design conference 2020,0
2. Return Loss Optimization of 25-Gbps High-Speed Serial Link on a Multilayer PCB
3. PCIe Gen-5 Desing Challenges of High-Speed Servers;vasa;2020 Electrical Performance of Electronic Package and systems (EPEPS),0
4. 112G Electrical System PerformanceStudy based on an improved SalzSNR Methodology;dong;DesignCon 2018,0
5. Statistical estimation of characteristic impedance distribution caused by PCB manufacturing process variation in high-speed mobile channels
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